Synopsys, Inc. (NASDAQ:SNPS), Mountain View, Calif., a world leader
in semiconductor design software, has announced that the Synopsys
Star-RCXT(TM) parasitic extraction solution has been qualified and
selected by more than 50 leading semiconductor companies to achieve
silicon-accurate sign-off for System-on-Chip (SoC), ASIC, memory, custom
digital and analog/mixed-signal 65-nanometer (nm) designs. Already
trusted for more than 125 successful 65-nm production tapeouts, the
Star-RCXT solution continues as the gold standard solution with the
industry's broadest 65-nm qualification and usage.
Companies that have qualified and selected the Star-RCXT solution
for use in their 65-nm sign-off and tapeout flows include Advanced Micro
Devices, Inc., Altera Corporation, Analog Devices, Inc., ARM, Avago
Technologies, Broadcom Corporation, Chartered Semiconductor
Manufacturing Ltd., the Common Platform Technology Alliance, Fujitsu
Limited, HiSilicon Technologies Co., Ltd. (former ASIC Design Center of
Huawei Technologies Co., Ltd.), Hynix Semiconductor, Inc., IBM, Icera
Semiconductor, Juniper Networks, Inc., LG Electronics, Marvell
Technology Group, Ltd., NEC Electronics, NVIDIA Corporation, P. A. Semi,
Inc., RealTek Semiconductor Corporation, Renesas Technology Corp.,
Samsung Electronics Company, Ltd., Solarflare Communications, Inc.,
Toshiba Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.,
United Microelectronics Corporation, Virage Logic Corporation, and
others.
"Our leading-edge customers at 65 nanometers are using the
Star-RCXT solution on the merits of its silicon-accurate modeling of
advanced process effects to achieve successful design tapeout,"
said Robert Hoogenstryd, director of Design Analysis and Sign-Off
Marketing at Synopsys. "Reaching this milestone of more than 50
customers and over 125 production tapeout successes at 65 nanometers
clearly shows that the Star-RCXT solution will continue its leadership
position as 65-nm process technology transitions into mainstream
production."
The Star-RCXT solution is the leading parasitic extraction solution
within Synopsys' Galaxy(TM) Design Platform, and the only
single-tool extraction solution to cover cell-based, memory, custom
digital, and analog/mixed-signal designs. The Star-RCXT solution
supports the advanced capabilities required by 65-nm design, including
process variation-aware modeling such as selective process biasing
(spacing- and width-dependent metal bias), chemical-mechanical polishing
(CMP) based effects including density and width-dependent thickness
variation, width-dependent temperature variation, micro-loading effect
and low-K dielectric damage. With efficient memory usage,
multi-CPU/multi-core distributed processing, adaptive extraction
algorithms and proprietary parasitic reduction capability, the Star-RCXT
solution provides extremely high performance and capacity while
generating the smallest and most sub-femtofarad accurate netlist
necessary to sign-off the world's largest SoC designs.
About Synopsys
bSynopsys, Inc. (NASDAQ:SNPS) is a world leader in electronic
design automation (EDA) software for semiconductor design. The company
delivers technology-leading system and semiconductor design and
verification platforms, IC manufacturing and yield optimization
solutions, semiconductor intellectual property and design services to
the global electronics market. These solutions enable the development
and production of complex integrated circuits and electronic systems.
Through its comprehensive solutions, Synopsys addresses the key
challenges designers and manufacturers face today, including power
management, accelerated time to yield and system-to-silicon
verification. Synopsys is headquartered in Mountain View, California,
and has more than 60 offices located throughout North America, Europe,
Japan and Asia.
For more information, visit http://www.synopsys.com or call
650/584-8635.
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