Small instruments with big performance.

Logic analyzers (LAs) are used to examine the simultaneous relationships among several digital signals. Both timing and state operating modes may be available on the same instrument. A state analyzer uses a clock provided by the DUT to acquire data. The clock is positioned relative to data transitions so only stable, settled data states are recorded.

In contrast, a timing analyzer uses a totally independent asynchronous clock generated internally by the LA. All incoming signals are simultaneously sampled by this clock, which typically runs at a much higher rate than the DUT logic being examined.

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A timing analyzer helps you prove that one signal changed a certain amount of time before another or that several signals all changed within some very small amount of time. State analyzers are used to track the various combinations of logic levels that existed among the channels. Whether one channel changed a nanosecond before or after another channel isn't relevant in a 100-MS/s state analyzer. It is relevant in a timing analyzer.

In both state and timing modes, sophisticated triggering helps you describe and capture only certain events. Large capture memories ensure that you can see events leading up to the trigger condition as well as subsequent events. The assumption is that you can determine why a system is behaving incorrectly or at least get valuable clues by examining conditions ahead of and after the trigger.

Modern LAs have built-in features to help in this examination process. You can set up a very detailed if-then-else trigger tree to accurately pinpoint erroneous events so that the errant byte or bytes quickly are found. Inevitably, given that you don't initially know what you are looking for, troubleshooting generally takes some time even with the best triggering systems.

Not surprisingly, this LA capability has become complex and includes multiple levels of programmable conditions. For example, the DigiView[TM] Model DV3400 has eight universal trigger match circuits and four configurable four-stage trigger sequencers. A trigger match circuit compares the incoming channel data to a predefined type and state.

For the DV3400, the available match types include pattern, edges, stable, equal, not equal, greater than, greater than or equal, less than, and less than or equal. After selecting the type of match, you enter a combination of 0, 1, and X (don't care) across all 18 or 36 channels.

As shown in Figure 1, the outputs of the eight match circuits then are combined and applied to a succession of sequencers. In the example shown, when stable states corresponding to the programmed values are present, outputs from match circuits 2 and 3 are combined via terms 2 and 3 and applied to the counters in sequencer 1. Match 2 conditions must be satisfied 1,024 times before term 3 is considered, and this condition must occur 64 times before sequencer 2 is enabled. The trigger is output only after all events occur the programmed number of times and in the predefined order.

Triggered data capture is a major LA attribute that relates to several low-level capabilities. According to Jerry Merrill, CEO of TechTools, source of the DigiView LAs, "Any LA, whether stand-alone or PC-based, must:

* Maintain the DUT's signal integrity.

* Accurately determine each signal's logic level relative to a threshold.

* Tolerate over/undervoltage conditions.

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* Store the data samples in real time.

* Optionally, compress the data samples in real time.

* Detect trigger conditions in real time.

* Detect buffer full and halt acquisition.

"After the data has been captured, the instrument is required to present it as waveforms, tables, or lists; measure and interpret the data during analysis; enable the data to be searched and saved or restored; and optionally support e-mail, remote printing, screen captures, and data exporting. A PC-based instrument also must transfer data quickly to the PC host," Mr. Merrill explained.

Stand-Alone vs. PC-Based

Cost and size are two obvious differences that distinguish these two forms of LAs, but so too are speed, memory length, and analysis flexibility. Often, PC-based LAs are only large enough to carry the required connectors and logic circuitry. USB-based analyzers are powered from the bus so the space usually taken by an on-board power supply is saved. In addition, many PC-based LAs integrate virtually all their functionality within a large FPGA, further minimizing the PCB space required.

If your DUT only has 32 or fewer logic lines and operates with a relatively slow clock, you may be able to use the $389 Intronix Model LA 1034 LogicPort LA shown in Figure 2. It has 34 input channels so you can capture a couple of control lines as well as 32 data signals and samples asynchronously from 1 kHz to 500 MS/s and synchronously from DC to 200 MS/s.

"The LA1034's logic and memory are entirely contained within a single FPGA," commented Harrison Young III, company CEO. "This keeps the speed up and the cost down compared with products having external memory interfaces. The LA1034's efficient lossless compression algorithm allows its buffer depth to be greatly extended with no loss in signal integrity."

Lossless signal compression is included in this product because its basic memory depth is 2,048 S/channel. To conserve memory, the LA 1034 only records data transitions.

Lossless data compression relies on redundancy within the data, which can be encoded to reduce storage requirements. The amount of compression possible depends on the nature of the data.

For example, the LA 1034 datasheet quotes a [2.sup.33]:1 maximum compression ratio or a factor of greater than eight billion. This degree of compression is possible for a signal starting with a single logic 1 followed by eight billion zeros. If your signals typically consist of a few fast pulses with lots of dead time, compression can be very useful. However, for very active signals with a large number of transitions, the effective compression ratio will be small.

In the LA 1034's favor, the datasheet clearly states a few key input parameters sometimes missing from low-cost LA specifications. State-mode setup and hold times refer to the length of time that the data must be settled to its final state before and after the sampling clock edge. The quoted 2.0-ns setup time and 0.0-ns hold time are consistent with 200-MS/s state sampling. Further, the 2-ns window can be adjusted [+ or -]2.5 ns, giving you much greater control of the relative position of the sampling instant.

Channel-to-Channel Skew

Also, a 0.6-ns typical skew and 1.0-ns maximum channel-to-channel skew are quoted. Few low-cost LAs deal with channel skew at all. Skew is important because it determines the degree to which displayed data timing can be believed.

If an analyzer specifies worst-case channel-to-channel skew of 1 ns, simultaneous transitions on channel A and channel B could appear to be 1 ns apart with either A or B leading the other. There could be as much as a 1-ns uncertainty between the fastest and slowest channels being sampled. There is a chance that an asynchronous sampling clock will fall during this 1-ns window depending on the relationship between the clock rate and the data rate.

If the sampling clock were derived from the DUT timing, then the sampling no longer could be considered asynchronous. A fixed relationship between the two clocks means that the LA actually would be operating with synchronous clocking.

It might be possible to arrange the phase of the sampling clock relative to that of the DUT timing so that samples never occurred during the 1-ns uncertainty period. This is an advantage of synchronous clocking for state data acquisition. Unless something goes terribly wrong, each acquisition is guaranteed to have occurred during periods when the data lines are settled and stable.

At the opposite extreme, although very unlikely, it is possible for an asynchronous sampling clock to be so closely aligned to the DUT timing that a large proportion of the samples falls during the 1-ns uncertainty period. On a DSO, this undesirable situation also is possible so these instruments deliberately offset the sampling clock phase between acquisitions to upset potential synchronism with the data. Unfortunately, if either a logic analyzer or a DSO captures only one long acquisition to memory, it could accidentally be made under nearly synchronous conditions.

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Typically, near-synchronous operation doesn't occur because the data timing and asynchronous sampling clock are independent. Nevertheless, when the clock rate in this example reaches 1 GS/s, you are guaranteed to catch each 1-ns transition period.

At faster rates, more than one sample always will fall in that period. The result can be acquisition of incorrect relationships between two or more data signals. You can't extract meaningful signal-to-signal timing information beyond the instrument's inherent skew limitations.

How can you ensure that the acquired data accurately reflects what actually occurred? One way is to attach a pair of probes to the same signal and observe the displayed traces as the sampling rate is increased. At some point you will see transitions on one signal lag those on the other. Now you know which channel is slower and by approximately how much. If you are working with only a few channels, you might adjust the lengths of the probe wires to partially compensate for the timing differences, reducing the overall skew.