Improving yield with retooling and robust infrastructure.

Everyone in the semiconductor industry is aware of one facet of Moore's law: the cost per function decreases every year. This concept allows semiconductor buyers to plan for periodic price reductions and requires semiconductor companies to factor in a learning curve for yield improvement.

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As production ramps from first silicon to full volume, the product yield becomes a significant contributor to overall company success. In an internal study, a large global integrated device manufacturer found that a yield increase of 1.7% caused a $2.38 million growth in earnings before interest and taxes over the lifetime of a single typical product.

It's becoming more difficult to achieve adequate yield, much less work on yield improvement, at advanced process technologies. At 130-nm and larger process nodes, the failures were mostly random defects, and the foundry working on its own could localize and fix the process issues that contributed to the defects.

Now, the latest nanometer processes are exhibiting new failure mechanisms. One class of defects includes the physical or mechanical issues related to the size of the features, such as bridging and resistive opens or shorts. Another class of failures is related to electrical parameters and results in problems such as noise, crosstalk, thermal parameter drift, voltage drop, and device variability.

Problems Facing Production

Foundries use test structures in the scratch area of the wafer to monitor production efficiencies. As processes migrate from development to production, these wafer acceptance test patterns show if the base parameters are within acceptable ranges. Now, it is becoming much more difficult to use these monitors in many of the newer processes for problem isolation.

Paradoxically, as the industry aggressively drives toward half- and quarter-node process strategies, it must now halve new process ramp times to maintain adequate time-to-volume production. To ease these problems, the contributors to process bring-up--design, test, and manufacturing--need a common data exchange platform and a data flow that enable quick changes in test vectors to address yield hot spots.

These issues come to a head at the process nodes below 90 nm. The latest processes are experiencing an explosion of design rules that now can number more than 4,000. These rule sets make eventual sign-off even more challenging because the design rules come in flavors--required, recommended, and optional--with some of the rules mutually exclusive to others in the sets.

At the early stages of process development, design rules and device model parameters are constantly changing as engineers make adjustments to the process flows. To cover the potential manufacturing issues, the foundries eventually release their design rules and device specifications in a process design kit that makes most of the parameters excessively conservative to ensure reasonable yields for themselves.

As scaling and material engineering continue to work on Moore's law, the resulting process requires changes in both the horizontal and vertical dimensions, and similar changes also must be applied to the gate-threshold voltages. The sub-90-nm process wafers have the threshold voltages for the high-speed variant set so low that the channel never turns completely off, resulting in fairly high leakage currents. In addition, because the gate oxides are so thin, the gates also contribute some tunneling current to the overall leakage.

To make design closures even more difficult, the problem of creating reproducible images on the photo resist when the images are smaller than the exposing wavelength requires significant modifications to the layout. These layout changes are generically classified as reticule enhance technologies and create other problems for designers.

The many layers of interconnect and their proximity cause the layout to have a large effect on the design quality and timing issues. Now, because of the imaging modifications, there even are rules to define exceptions to other rules and to address the forbidden zones in the mask preparation steps that result from the modifications and physics of light.

In an ideal world, the final device models would correlate exactly with the silicon, and everything would be stable. In reality, the latest processes suffer from variation at all possible levels: wafer-to-wafer, die-to-die, and transistor-to-transistor. These variations result from pattern sensitivity and manufacturing process complexity leading to atomic-level differences and greater parametric disparities. The interaction of the device parameters with the layout further clouds the picture, causing greater levels of uncertainty.

An IP-Driven Solution for 90 nm and 65 nm

Due to their density, regular structures, and increasing popularity on the die, memories commonly are used by foundries and semiconductor companies for process ramping and yield learning. As a part of the process ramp and yield learning curve for 90 nm, 65 nm, and 55 nm, a new approach to semiconductor manufacturing has been deployed, offering a yield-acceleration flow that enables significant reductions in silicon test, silicon bring-up, and time-to-volume production.

To meet the needs of the many types of memory applications, Virage Logic designs memories with very flexible and comprehensive built-in self-test (BIST). The memory BIST (MBIST) includes test algorithm programmability and the capabilities to execute test at the functional speed of the design and change memory-timing parameters such as the self-timed clocks (Figure 1).

All test chips are designed using an industry-standard semicustom ASIC design flow from the register transfer level (RTL) to the graphic data system (GDS). This flow follows well-defined processes, and each has been optimized to reduce design cycle time.

Traditional practice at the foundries has been to completely separate the various areas of domain expertise. The foundry knows the process and physical issues related to the silicon while the designers know the integrated functionality. This knowledge segmentation resulted from the belief that both parties need to protect their proprietary information and intellectual property.

To provide greater insight into the various yield issues during process bring-up, engineers can rely on new software tools to analyze tester data logs and provide results in a user-friendly format. These tools can automatically search for any error trends and supply guidelines for their correction by analyzing the volumes of data and facilitating cross probing of the design, model, and layout files.

Although the testers and characterization teams generate large volumes of data, not all is relevant to all parties, so the tools have encryption and access restriction capabilities built in. Data is transferred via the ubiquitous Web infrastructure to enable a standards-based data exchange.

A Study in Improved Yield Learning

By deploying a memory-centric silicon verification process that includes the memories, BIST, and other support circuitry as well as the critically important software tools to analyze the volumes of test data, design and process engineers have improved the yield learning curve. Memories become the central design, test, and process evaluation block due to their density, regular structures, and capability to generate various size function blocks on a chip. By reducing the time for test modifications and improving data feedback, chipmakers can significantly reduce the time for production ramp while improving overall yields.

Yield-accelerating IP treats process bring-up as a series of development and test phases. By identifying three separate phases in the evaluation, appropriate resources can be dedicated to the problems.

In Phase 1, quick BIST vectors are executed on the multiple dies to identify yield hot spots at the wafer or die level. A hot spot occurs where the defect density/bit cell is higher than the average of a given threshold value. If Phase 1 indicates a wafer-level yield trend, then a process issue has been identified, and the foundry needs to identify and correct the process problems.

If no wafer level yield trend is identified in Phase 1, further analysis commences by executing additional vectors on the failed dies to collect more detailed information related to the hot spots. The process engineer tries to isolate the problems to the memory IP or to a design issue external to the memory in Phase 2. Non-memory design issues are corrected in the normal design correction flows.

If the problems are identified as memory IP issues, then Phase 3 comes into play. The software performs detailed bitmap and fault isolation.

More intensive test patterns can be generated to completely stress the areas of interest. This flow automatically identifies fault types and provides detailed statistical data of categorized fault occurrences through complementary software tools. This memory-centric manufacturing ramp-up flow is important for early process learning because most of the yield-limiting factors can be addressed and repaired before full-volume manufacturing begins. The capability to identify, evaluate, and address production issues before volume production saves test wafers and reduces time-to-process release.